On October 25th, Fujitsu officially announced the upcoming release of its Sparc64VI+ processor, codenamed Jupiter, which will integrate four cores into a single chip in 2008.
This new generation of chips will be developed using Fujitsu’s proprietary manufacturing process, implementing 65-nanometer technology, as stated by Mr. Takumi Maruyama, Fujitsu’s director in charge of enterprise server development.
The Sparc64 chip line is known for its reliability, yet it has not been widely adopted outside of the Japanese market. However, in 2004, Fujitsu partnered with Sun Microsystems to integrate this chip generation into the development of the Advanced Processor Line (APL) high-end server series. This alliance officially commenced operations at the end of 2006 with the launch of the dual-core Sparc64 VI server series, codenamed Olympus.
Maruyama indicated that the architectural design for the Olympus chip generation has been finalized, and production has begun. Nevertheless, this chip line is being released one year later than the manufacturer’s initial plan—two years ago, Fujitsu anticipated launching the Olympus chip in the latter half of 2005.
Both the Sparc64 VI and VI+ chips share the same system bus frequency, enabling the new processor generation to serve as an upgrade for older machines. The manufacturer also ensures that, despite using a low bus, there remains sufficient memory bandwidth to run all four chip cores simultaneously.
Each core of the Sparc64 VI+ chip can handle two separate threads at the same time. Fujitsu refers to this as VMT (Vertical Multithreading) technology. “VMT technology can enhance the performance of the processor by an additional 20%,” Maruyama stated.
The Sparc64 VI chip will be capable of processing four threads simultaneously, while the VI+ can handle eight different threads. Based on this foundation, Fujitsu plans to develop a new generation of multi-core, multi-threaded processors.
Simultaneously, Fujitsu’s partner in the alliance, Sun, is also developing its own multi-core processor generation, expected to be introduced in early 2006 with the codename Niagara.
HVD
